1. Field of the Invention
The present invention relates in general to serial-to-parallel data conversion and transmission devices. In particular, the present invention relates to serial to parallel data conversion and transmission device for direct transmission to a receiving device without the intervention of a processor.
2. Technical Background
Conventional serial-to-parallel data conversion and transmission devices are widely employed in data communication devices. For example, in a computer system receiving remote data via the telephone network, a serial-to-parallel data conversion and transmission device would convert serially transmitted information bits sent from a remote system and received at the local end into multi-bit, for example, bytes of data, and subsequently send the received multi-bit, or, in other words, parallel data to other sections in the computer system for processing.
FIG. 1 of the accompanying drawings is a schematic block diagram showing the conventional scheme for serial-to-parallel data conversion and transmission. As shown, a device A sends data to another device B over a serial data communication line DA. For example, device A and B may be personal computers, and the serial data communication line DA may be a local connection, e.g., an RS-232A bus.
Device A transmits data over the serial data link DA to device B, and the received data is converted from serial to parallel data format and stored in one of the receivers 142, 144, 146 and 148. A data conversion and transmission device 10, such as a shift register-based device, receives the incoming serial data, converts the data from serial to parallel format, and sends the data to a processor 12, such as a CPU of device B, which assigns the data to one of the receivers 142, 144, 146 and 148 for storage.
Referring to FIG. 2 of the drawings, a timing diagram of the material signals in the serial-to-parallel data conversion and transmission scheme of FIG. 1 is shown for describing the operation of a conventional device. The operation of data conversion and transmission is as follows.
(1) When an active-high chip select signal CS, e.g., a logic one, is issued, device A is prohibited from transmitting data to device B. PA1 (2) When signal CS changes and remains in the logic zero state, and a clock signal CK changes from logic zero to logic one, device A is permitted to send data to device B. PA1 (3) When clock signal CK changes from logic one to logic zero while chip-select CS signal remains at logic zero, the data sent over data line DA is stored in the data conversion and transmission device 10. PA1 (4) Steps (2) and (3) are repeated for each bit supplied on data line DA. PA1 (5) Processor 12 in device B passes the data stored in data conversion and transmission device 10 in parallel form to receiver 142, 144, 146 or 148.
In the above-described conventional scheme of serial-to-parallel data conversion and transmission, system processor 12 (usually the CPU of device B) is required to intervene in order to supply data stored in data conversion and transmission device 10 to one of the receivers. This requirement not only adds to the load of the CPU of a computer system, but also reduces data transmission throughput in this serial-to-parallel data conversion and transmission system, since a heavily loaded processor must utilize critical time to process the required receiver assignment.